library verilog;
use verilog.vl_types.all;
entity cpu is
    port(
        out1            : out    vl_logic_vector(15 downto 0);
        clock           : in     vl_logic;
        reset           : in     vl_logic;
        load            : in     vl_logic;
        incre           : in     vl_logic
    );
end cpu;
